单周期CPU

module ctr(
    input [5:0] opCode,//
    input [5:0] funct,//
    output reg regDst,//
    output reg aluSrcA,//
    output reg [1:0] aluSrcB,//
    output reg memToReg,//
    output reg regWrite,//
    output reg memRead,//
    output reg memWrite,//
    output reg branch,//
    output reg [2:0] aluop,//
    output reg jmp,
    output reg jal,
    output reg jr,
    output reg lui,
    output reg shift,
    output reg bne,
    output reg bltz,
    output reg bgtz,
    output reg imm_expand,
    output reg [1:0] flag
);

always @(opCode,funct) 
begin
    case(opCode)
    
        6'b001001: 
        begin
            regDst = 0;    
            aluSrcA = 1'b1;//
            aluSrcB = 2'b01;//
            memToReg = 0;  //
            regWrite = 1;  //
            memRead = 0;   //
            memWrite = 0;  //
            branch = 0;    //
            aluop = 3'b000;//
            jmp = 0;
            jal=0;
            jr=0;
            lui=0; 
            bne=0;
            bltz=0;
            bgtz=0;   
            shift=0;
            imm_expand=0; 
            flag=2'b11;       
        end             
       /*
       以上为控制单元对某一条指令得出控制信号的代码示例，根据输入的opCode,funct得出各个控制信号并输出。
       */
end
endmodule

module aluctr(
    input [2:0] ALUOp,
    input [5:0] funct,
    output reg [3:0] ALUCtr
);
always @(ALUOp or funct)  
    casex({ALUOp, funct}) 
        //非R型
        9'b000xxxxxx: ALUCtr = 4'b0010; // add
        9'b001xxxxxx: ALUCtr = 4'b0110; // sub
        9'b010xxxxxx: ALUCtr = 4'b0000; // and
        9'b011xxxxxx: ALUCtr = 4'b0001; // or
        9'b100xxxxxx: ALUCtr = 4'b0100; // xor
        9'b101xxxxxx: ALUCtr = 4'b0111; // slt
        9'b110xxxxxx: ALUCtr = 4'b1100; // lui
        //R型
        9'b111_100000: ALUCtr = 4'b0010; // add
        9'b111_100001: ALUCtr = 4'b0010; // addu
        9'b111_100010: ALUCtr = 4'b0110; // sub
        9'b111_100100: ALUCtr = 4'b0000; // and
        9'b111_100111: ALUCtr = 4'b0101; // nor
        9'b111_100101: ALUCtr = 4'b0001; // or
        9'b111_100110: ALUCtr = 4'b0100; // xor
        9'b111_101010: ALUCtr = 4'b0111; // slt  
                                          
        9'b111_000100: ALUCtr = 4'b0011; // sllv
        9'b111_000110: ALUCtr = 4'b1000; // srlv
        9'b111_000111: ALUCtr = 4'b1111; // srav  
        
        default:ALUCtr = 4'b0010;
    endcase
endmodule

module alu( 
input [31:0] input1, 
input [31:0] input2, 
input [3:0] aluCtr, 
output reg[31:0] aluRes, 
output reg zero 
); 
always @(input1 or input2 or aluCtr)
begin 
case(aluCtr) 

4'b0110: // 减
begin 
  aluRes = input1 - input2; 
  if(aluRes == 0) 
  zero = 1; 
  else 
  zero = 0; 
end 
  
4'b1100: // lui
aluRes =input2 << 16;

4'b0010: // 加
aluRes = input1 + input2; 
  
4'b0100: // 异或
aluRes = input1 ^ input2; 
  
4'b0000: // 与
aluRes = input1 & input2; 
  
4'b0001: // 或
aluRes = input1 | input2; 
  
4'b0101: // 或非
aluRes = ~(input1 | input2); 
  
4'b0011: // 左移
aluRes = input1 << input2; 
  
4'b1000: // 逻辑右移
aluRes = input1 >> input2;
  
4'b1111: // 算术右移
aluRes = $signed(input1) >> input2; 
  
4'b0111: // 小于设置
begin 
  if(input1<input2) 
  aluRes = 1; 
  else
  aluRes = 0; 
end 
  
default: 
aluRes = 0; 
endcase 
end 
  
endmodule 

module regFile( 
	input clk, 
	input reset, 
  input [31:0] regWriteData, //写寄存器的值
  input [4:0] regWriteAddr, //写寄存器时寄存器的地址
  input regWriteEn,	//写寄存器使能
  input [4:0] RsAddr,	//RS寄存器地址
  input [4:0] RtAddr,		//RT寄存器地址
	output [31:0] RsData,	//RS寄存器的值
  output [31:0] RtData  //RT寄存器的值
);
  
reg[31:0]regs[0:31]; //寄存器组
  
//根据地址读出 Rs、Rt 寄存器数据
assign RsData = (RsAddr == 5'b0 ) ? 32'b0 : regs[RsAddr]; 
assign RtData = (RtAddr == 5'b0 ) ? 32'b0 : regs[RtAddr]; 
integer i;
  
always @( posedge clk ) //时钟上升沿操作
begin
    if(!reset) 
    begin
        if(regWriteEn == 1) //写使能信号为1时写操作
        begin
         regs[regWriteAddr] = regWriteData; //写入数据
        end
    end
    else 
    begin
         for(i = 0; i < 32; i = i + 1)
         regs[i] = 0; //重置时所有寄存器赋值为0，复位       
    end
end
endmodule

irom imem (
  .clka(clka),    // 时钟输入
  .ena(ena),      // 使能信号
  .addra(addra),  // 指令所在地址
  .douta(douta)  // 对应指令输出
);

module dram (
  input clk, 
  input we,
  input re,
  input reset,
  input [1:0] flag,//00-> byte 01->half word  1x->word
  input [7:0] addr, 
  input [31:0] wd,
  output [31:0] rd
);
			 	 
reg [7:0] RAM[255:0]; 

//read
assign rd=re && flag[1]? 
{ {RAM[a+3]},{RAM[a+2]},{RAM[a+1]},{RAM[a+0]}} : //字
( 
    re && flag[0]?
    { {16{RAM[a+1][7]}} ,{RAM[a+1]},{RAM[a]} }://半字
    { {24{RAM[a][7]}} ,RAM[a]} //字节
);

//write
integer i;
always @ (posedge clk,posedge reset)
begin
    if(reset)begin
        for(i = 0; i < 256; i = i + 1) 
            RAM[i]=0;       
    end	
    else if (we) begin
        if(flag==2'b00)//字节
        begin
            RAM[a]=wd[7:0];
        end
        else if(flag==2'b01 )//半字
        begin
            { {RAM[a+1]},{RAM[a]} }=wd[15:0];
        end
        else if(flag[1])//字
        begin
            { {RAM[a+3]},{RAM[a+2]},{RAM[a+1]},{RAM[a+0]}}=wd;
        end           
    end  
end
endmodule

module Shifter(
		input [31:0] SHIN,
		input [4:0]  Sa,//sa
		input        ShiDir,
		input        Arith,
		output reg [31:0] SHOUT
    );

	always @(*) begin
		if (!ShiDir)      SHOUT = SHIN << Sa ;//逻辑左移
		else if (!Arith) SHOUT = SHIN >> Sa;//逻辑右移
		else       SHOUT = $signed(SHIN) >>> Sa;//算数右移
	end	

endmodule

module signext( 
input [15:0] inst, // 输入16位
input imm_expand,
output [31:0] data // 输出32位
); 
// 根据符号与立即数扩展方式补充符号位
assign data = imm_expand && inst[15:15]?{16'hffff,inst}:{16'h0000,inst}; 
endmodule 

module display(clk,data,sm_wei,sm_duan); 

input clk;
input [15:0] data; 
output [3:0] sm_wei; 
output [6:0] sm_duan;
//分频 

integer clk_cnt;
reg clk_400Hz; 
always @(posedge clk)

if(clk_cnt==32'd100000)
begin 
    clk_cnt <= 1'b0; 
    clk_400Hz <= ~clk_400Hz;
end 
else 
clk_cnt <= clk_cnt + 1'b1; 

//位控制
 
reg [3:0]wei_ctrl=4'b1110; always @(posedge clk_400Hz)
wei_ctrl <= {wei_ctrl[2:0],wei_ctrl[3]}; 

//段控制 

reg [3:0]duan_ctrl;
always @(wei_ctrl)
case(wei_ctrl) 
4'b1110:duan_ctrl=data[3:0]; 
4'b1101:duan_ctrl=data[7:4]; 
4'b1011:duan_ctrl=data[11:8];
4'b0111:duan_ctrl=data[15:12];
default:duan_ctrl=4'hf;
 endcase
 
//解码模块 

reg [6:0]duan;
 
always @(duan_ctrl) 
case(duan_ctrl) 
4'h0:duan=7'b100_0000;//0 
4'h1:duan=7'b111_1001;//1 
4'h2:duan=7'b010_0100;//2 
4'h3:duan=7'b011_0000;//3 
4'h4:duan=7'b001_1001;//4 
4'h5:duan=7'b001_0010;//5 
4'h6:duan=7'b000_0010;//6 
4'h7:duan=7'b111_1000;//7 
4'h8:duan=7'b000_0000;//8 
4'h9:duan=7'b001_0000;//9 
4'ha:duan=7'b000_1000;//a 
4'hb:duan=7'b000_0011;//b 
4'hc:duan=7'b100_0110;//c 
4'hd:duan=7'b010_0001;//d 
4'he:duan=7'b000_0111;//e       
4'hf:duan=7'b000_1110;//f
default : 
duan = 7'b100_0000;//0
endcase

assign sm_wei = wei_ctrl; 
assign sm_duan = duan; 
endmodule

assign mux1 = reg_dst ? inst[15:11] : inst[20:16]; 
//得到写回寄存器rd/rt
assign mux2 = alu_srcA ? expand : RtData; 
//得到立即数/寄存器rd
assign mux6 = shift ? shiftRe : aluRes;
//得到移位结果/ALU结果
assign mux3 = memtoreg ? memreaddata : mux6; 
//得到写回寄存器的数值来自内存/来自计算结果
assign mux7 = jr ? {RsData, 2'b00} : jmpaddr;
//得到跳转地址来自寄存器/指令内26位地址
assign mux5 = jmp ? mux7 : mux4;
//得到跳转地址/分支地址
assign choose5 = bne ? ~zero : zero;
//得到bne的判断结果
assign choose4 = branch & choose5; 
//得到是否分支指令
assign mux4 = choose4 ? address : add4; 
//得到是否分支指令

assign jmpaddr = {add4[31:28], inst[25:0], 2'b00}; 
//指令内26位地址
assign expand2 = expand << 2; 
assign address = pc + expand2; 
//PC+4

module top( 
input Clk, 
input reset,
output [6:0] seg,
output [3:0] sm_wei
); 
// 指令寄存器pc 
reg[31:0] pc;
reg[31:0] add4; 
wire choose4, choose5; 

// 复用器信号线
wire[31:0] expand2, mux2, mux3, mux4, mux5,mux6,mux7,mux8,mux9, address, jmpaddr; 
wire[4:0] mux1; 
wire [31:0] inst;

// CPU控制信号线
wire reg_dst, jmp, branch, memread, memwrite, memtoreg; 
wire regwrite; 
wire[2:0] aluop; 
wire alu_srcA;

// ALU信号线
wire zero; 
wire[31:0] aluRes; 

// ALU控制信号线
wire[3:0] aluCtr;

// 内存信号线
wire[31:0] memreaddata; 

// 寄存器信号线
wire[31:0] RsData, RtData; 

// 扩展信号线
wire[31:0] expand; 

//拓展
wire jr;   
wire shift;
wire lui;
wire bne;
wire [31:0] shiftRe;
wire imm_expand;
wire [1:0] flag;

//分频得到clkin  
integer clk_cnt;
reg clkin;
always @(posedge Clk)
if(clk_cnt==32'd75_000_000) 
begin
clk_cnt <= 1'b0; 
clkin <= ~clkin;
end 
else
clk_cnt <= clk_cnt + 1'b1;

always @(negedge Clk) // 时钟下降沿操作
    begin 
    if(!reset) 
    begin
        pc = mux5; // 计算下一条pc，修改pc 
        add4 = pc + 4; 
    end 
else 
    begin
    pc = 32'b0; // 复位时pc写0 
    add4 = 32'h4; 
    end 
end 

// 实例化控制器模块
ctr mainctr( 
.opCode(inst[31:26]), 
.funct(inst[5:0]), 
.regDst(reg_dst), 
.aluSrcA(alu_srcA), 
.memToReg(memtoreg), 
.regWrite(regwrite), 
.memRead(memread), 
.memWrite(memwrite), 
.branch(branch), 
.aluop(aluop), 
.jmp(jmp),
.jal(jal),
.jr(jr),
.lui(lui),
.shift(shift),
.bne(bne),
.bltz(bltz),
.bgtz(bgtz),
.imm_expand(imm_expand),
.flag(flag)
); 

// 实例化ALU模块
alu alu(
.input1(RsData), 
.input2(mux2), 
.aluCtr(aluCtr), 
.zero(zero), 
.aluRes(aluRes));

// 实例化ALU控制模块
aluctr aluctr1( 
.ALUOp(aluop), 
.funct(inst[5:0]), 
.ALUCtr(aluCtr)
); 

// 实例化dmem模块
dram dmem( 
.clk(!clkin), 
.we(memwrite), 
.re(memread),
.reset(reset),
.flag(flag),
.a(aluRes[7:0]), 
.wd(RtData), 
.rd(memreaddata) 
); 

// 实例化imem模块
irom imem( 
.clka(!clkin),    // input wire clka
.ena(1'b1),      // input wire ena
.addra(pc[6:2]),  // input wire [4 : 0] addra
.douta(inst)  // output wire [31 : 0] douta
); 

// 实例化寄存器模块
regFile regfile( 
.RsAddr(inst[25:21]), 
.RtAddr(inst[20:16]), 
.clk(!clkin), 
.reset(reset), 
.regWriteAddr(mux1), 
.regWriteData(mux3), 
.regWriteEn(regwrite), 
.RsData(RsData), 
.RtData(RtData) 
); 

//实例化移位模块
Shifter shifte(
.SHIN(RtData),//rt
.Sa(inst[10:6]),//shamt
.ShiDir(inst[1:1]),
.Arith(inst[0:0]),
.SHOUT(shiftRe)//结果->rd
 );

// 实例化符号扩展模块
signext signext(
.inst(inst[15:0]), 
.imm_expand(imm_expand),
.data(expand)); 

//复用器
assign jmpaddr = {add4[31:28], inst[25:0], 2'b00}; 
assign mux1 = reg_dst ? inst[15:11] : inst[20:16]; 
assign mux2 = alu_srcA ? expand : RtData; 
assign mux6 = shift ? shiftRe : aluRes;; 
assign mux3 = memtoreg ? memreaddata : mux6; 
assign mux7 = jr ? {RsData, 2'b00} : jmpaddr;
assign mux5 = jmp ? mux7 : mux4;
assign choose5 = bne ? ~zero : zero;
assign choose4 = branch & choose5; 
assign mux4 = choose4 ? address : add4; 
assign expand2 = expand << 2; 
assign address = pc + expand2; 

//实例化数码管显示模块
smg_ip_model display (
.clk(Clk),
.sm_wei(sm_wei),
.data(mux6[15:0]),
.sm_duan(seg)
);
  
endmodule 

module topsim;
// Inputs 
reg clkin;
reg reset;
// output
wire [31:0] inst;
wire [31:0] pc;
wire [2:0] aluop;
wire alu_srcA;
wire [31:0] add4;
wire choose4;
wire reg_dst; 
wire jmp; 
wire branch; 
wire memread; 
wire memwrite;
wire memtoreg; 
wire regwrite;
wire zero;
wire [31:0] aluRes;
wire [3:0] aluCtr;
wire [31:0] memreaddata;
wire [31:0] RsData;
wire [31:0] RtData;
wire [31:0] expand2,expand;
wire[31:0] shiftRe;
wire[31:0]  mux2, mux3, mux4, mux5,mux6, address, jmpaddr; 
wire[4:0] mux1; 
wire imm_expand;
wire shift;
wire [1:0] flag;
// Instantiate the Unit Under Test (UUT) 

//调用top模块
top uut( 
.Clk(clkin),
.reset(reset),
.inst(inst),
.pc(pc),
.aluop(aluop),
.alu_srcA(alu_srcA),
.add4(add4),
.choose4(choose4),
.reg_dst(reg_dst),
.jmp(jmp),
.branch(branch), 
.memread(memread),
.memwrite(memwrite),
.memtoreg(memtoreg),
.regwrite(regwrite),
.zero(zero),
.shift(shift),
.aluRes(aluRes),
.aluCtr(aluCtr),
.shiftRe(shiftRe),
.memreaddata(memreaddata),
.RsData(RsData),
.RtData(RtData),
.expand(expand),
.expand2(expand2), 
.mux2(mux2),
.mux3(mux3), 
.mux4(mux4), 
.mux5(mux5), 
.mux6(mux6), 
.address(address), 
.jmpaddr(jmpaddr),
.mux1(mux1),
.imm_expand(imm_expand),
.flag(flag)
);

initial begin 
// Initialize Inputs 
clkin = 0; 
reset = 1; 
// Wait 100 ns for global reset to finish 
#100; 
reset = 0; 
end 
parameter PERIOD = 20; 
always begin 
clkin = 1'b0; 
#(PERIOD / 2) clkin = 1'b1; 
#(PERIOD / 2) ; 
end 
endmodule